1. Field of the Invention
This invention relates to a process for manufacturing a semiconductor device and, more particularly, to a semiconductor process for removing defects due to edge chips of a semiconductor wafer and semiconductor device fabricated thereby.
2. Description of the Related Art
Most semiconductor chips are formed in a circle-shaped semiconductor wafer. Therefore, the semiconductor chips located at the edge of the semiconductor wafer may have abnormal patterns. This is due to a defocus or the like that occurs during a photolithography process for forming predetermined patterns in the edge of the semiconductor wafer.
FIGS. 1 through 6 are cross-sectional views illustrating a conventional semiconductor process for forming DRAM devices on a semiconductor wafer. In the drawings, reference characters “A” and “B” represent a main chip area formed in an inside region of the semiconductor wafer and an edge chip area formed in an edge of the semiconductor wafer, respectively.
Referring to FIG. 1, an interlayer dielectric layer 3 and an etch stop layer 7 are sequentially formed on a semiconductor wafer 1. The etch stop layer 7 and the interlayer dielectric layer 3 are patterned to form main chip buried contact holes in the main chip area A and edge chip buried contact holes in the edge chip area B. Main chip buried contact plugs 5a and edge chip buried contact plugs 5b are formed in the main chip buried contact holes and in the edge chip buried contact holes, respectively. A molding layer such as a molding oxide layer 9 is formed on an entire surface of the semiconductor wafer 1 having the buried contact plugs 5a and 5b. A photoresist layer 11 is coated on the molding oxide layer 9. As illustrated in FIG. 1, the photoresist layer 11 has a non-uniform thickness throughout the wafer 1. In other words, the photoresist layer over the edge region of the wafer 1 may be formed to be thicker than the photoresist layer over the inside region of the wafer 1.
Subsequently, the photoresist layer 11 over the edge of the wafer 1 is selectively exposed and removed to expose the molding oxide layer 9 in the edge of the wafer 1. The edge exposure process is for preventing a clamp that contacts with the edge of the wafer from being contaminated by the photoresist layer during a subsequent dry etching process. The exposed edge molding oxide layer has a width of We. Preferably, the width We is minimized to increase the number of effective chips formed at the wafer 1. Therefore, although the photoresist layer 11 over the edge of the wafer 1 is selectively removed, the remaining photoresist layer 11 over the wafer 1 may be still non uniform.
The remaining photoresist layer is then exposed and developed using a storage node mask. Consequently, first storage node openings 11a and second storage node openings 11b are formed in the main chip area A and in the edge chip area B respectively. The first storage node openings 11a exhibit normal profiles that expose the molding oxide layer 9 in the main chip area A, whereas the second storage node openings 11b exhibit abnormal profiles that do not expose the molding oxide layer 9 in the edge chip area B. This phenomenon is due to the uneven thickness of the photoresist layer as described above. In other words, the exposure process with the storage node mask is performed within a predetermined focus latitude that is suitable for the uniform thickness of the photoresist layer 11 in the main chip area A. Accordingly, it is difficult to optimize the focus latitude of light irradiated onto the edge chip area B. As a result, defocus occurs in the edge chip area B and the second storage node openings 11b show abnormal profiles. In addition, the defocus phenomenon in the edge chip area B may be due to the uneven surface profiles on the edge of the wafer 1, especially, on a bevel region of the wafer 1.
Referring to FIG. 2, the molding oxide layer 9 and the etch stop layer 7 are etched using the photoresist layer 11 having the first storage node openings 11a and the second storage node openings 11b as an etch mask. As a result, first storage node holes 13a exposing the main chip buried contact plugs 5a are formed in the main chip area A. However, second storage node holes 13b having abnormal profiles are formed in the edge chip area B. As shown in FIG. 2, the second storage node holes 13b do not expose the edge chip buried contact plugs 5b. This is due to the abnormal profiles of the second storage node openings 11b. The photoresist layer 11 is then removed.
Referring to FIG. 3, a polysilicon layer and a sacrificial layer formed of a material such as oxide are sequentially formed on an entire surface of the semiconductor wafer 1 having the first and second storage node holes 13a and 13b. The polysilicon layer is conformally formed, and the sacrificial oxide layer is formed to a sufficient thickness to fill the first and second storage node holes 13a and 13b. The polysilicon layer and the sacrificial oxide layer are etched back until a top surface of the molding oxide layer 9 is exposed. As a result, first cylindrical storage nodes 15a are respectively formed in the first storage node holes 13a, and second cylindrical storage nodes 15b are respectively formed in the second storage node holes 13b. Further, sacrificial oxide layer patterns 17 remain in the first and second storage nodes 15a and 15b. As shown in FIG. 3, the second storage nodes 15b adjacent to the edge of the wafer 1 are not in contact with the edge chip buried contact plugs 5b. 
Referring to FIG. 4, the molding oxide layer 9 and the sacrificial oxide layer patterns 17 are removed using a wet etching process. Accordingly, inner walls and outer sidewalls of the first and second storage nodes 15a and 15b are exposed. The second storage nodes 15b adjacent to the edge of the wafer 1 may be lifted during the wet etching process for removing the molding oxide layer 9 and the sacrificial oxide layer patterns 17. The second storage nodes 15b, which are lifted from the surface of the wafer, are adhered onto the surface of the main chip area A, thereby acting as particle sources.
Referring to FIG. 5, a dielectric layer 19 and a plate conductive layer are sequentially formed over the semiconductor wafer 1 where the molding oxide layer 9 and the sacrificial oxide layer patterns 17 are removed. The plate conductive layer and the dielectric layer 19 are patterned to form a first plate electrode 21a and a second plate electrode 21b that cover a cell array area in the main chip area A and a cell array area in the edge chip area B, respectively. Consequently, as shown in FIG. 5, the cell array area adjacent to the edge of the wafer 1 has a relatively low surface profile as compared to a normal cell array area (cell array area in the main chip area A). In other words, there exists a step difference H between a top surface of the plate electrode (21a of FIG. 5) in the normal cell array area and a top surface of the plate electrode (21b of FIG. 5) in the abnormal cell array area. An upper interlayer dielectric layer 23 is formed over the semiconductor wafer having the first plate electrode 21a and the second plate electrode 21b. The upper interlayer dielectric layer 23 is generally formed of a flowable oxide layer such as a BPSG (boro-phosphor-silicate glass) layer. Nevertheless, the upper interlayer dielectric layer 23 also has an uneven surface profile, which is due to the step difference H.
Referring to FIG. 6, the uneven surface profile of the upper interlayer dielectric layer 23 may lead to a difficulty in a subsequent photolithography process. Accordingly, there is a need to planarize the upper interlayer dielectric layer 23 using a planarization process such as a chemical mechanical polishing (hereinafter, referred to as “CMP”) process. However, when the upper interlayer dielectric layer 23 having the uneven surface is planarized using the CMP process, an upper corner C of the plate electrode in the normal cell array area adjacent to the abnormal cell array area may be exposed as shown in FIG. 6.
As discussed above, the storage nodes in the cell array area that is adjacent to the edge of the wafer may be lifted during a subsequent wet etching process. The storage nodes, which are lifted, are adhered onto the normal main chip area, thereby acting as particle sources.
Accordingly, the manufacturing yield of semiconductor devices is significantly reduced. Moreover, the abnormal area where the storage nodes are lifted has a lower surface than the normal cell array area. Thus, the storage nodes in the normal cell array area may be exposed during a subsequent planarization process.